1. Field of the Invention
The present invention generally relates to silicon on insulator (SOI) wafer production and, more particularly, to the simultaneous production of multiple SOI wafers.
2. Background Description
Silicon on insulator (SOI) wafers are typically used in special applications such as, for example, static random access memories (SRAMs), and more recently for high performance complementary metal oxide semiconductor (CMOS) and dynamic random access memory (DRAM) applications. FIG. 1 shows a conventional SOI wafer cross section having an insulating layer 15 formed on a substrate 10 and a device layer 20 formed on the insulating layer 15.
The SOI wafers are typically manufactured by one of two processes. For example, the SOI wafers can be manufactured by (i) implanted oxygen (SIMOX) in which oxygen is implanted into silicon and converted into a silicon dioxide (SiO.sub.2) buried layer or (ii) wafer bonding and etch-back (BESOI) in which two wafers are bonded with oxide surface layers and one wafer is thinned to leave a thin device layer. In some versions of BESOI processing, etch stop layers are used in conjunction with chemical mechanical-polishing (CMP) to improve thickness and uniformity control. The BESOI process is costly and complex since it uses two wafers (a device quality wafer and a supporting wafer) for each resulting SOI wafer, and the additional process of etching back the supporting wafer (which does not form any part of the final product) when manufacturing the SOI wafer.
Another recent process for producing SOI substrates is the Smart-Cut.TM. process as described in U.S. Pat. No. 5,374,564, which is incorporated by reference in its entirety into the present application. The Smart-Cut.TM. process uses a hydrogen layer that is implanted prior to bonding, and an annealing process to fracture the bulk silicon after bonding to leave behind a thin layer. CMP is used to planarize and minimize non-uniformity of the cut SOI wafer.
More specifically and as described in U.S. Pat. No. 5,374,564, the Smart-Cut.TM. process includes processing a device wafer to have a quality surface layer. An oxide layer is provided over the device layer, and a buried hydrogen-rich layer is implanted at a certain depth. A "handle wafer" with or without an oxide surface is provided, and the device wafer is flipped and the surfaces are bonded. The structure is annealed to form connecting voids from hydride formation. The structure is then fractured, and the transferred device layer is CMP polished and cleaned.
Although the art of producing SOI wafers is well developed, there remain some problems inherent in this technology. One particular problem is that it is difficult to provide thickness uniformity across the device layer of the wafer. Another problem inherent in this technology is the need for two wafers (e.g., a supporting wafer and a device quality wafer) when forming a single SOI wafer. This latter problem greatly increases the cost and complexity of manufacturing SOI wafers.
The lack of thickness uniformity is mainly due to the need for polishing, such as CMP, to smooth the surface of the device layer. To overcome this problem, U.S. Pat. No. 5,882,987 incorporated herein in its entirety into the present application has devised a method for forming a thin device layer. This is accomplished by providing an etch stop layer beneath the device layer in the starting substrate. The etch stop layer eliminates the need for CMP such that the device thickness, uniformity and smoothness are based on the deposited film and not on the CMP.
More specifically, FIGS. 5A-5G of U.S. Pat. No. 5,882,987 show the formation of an etch stop layer on a first wafer and an epitaxial device layer formed on the etch stop layer. A bonding layer is formed on the device layer. Ions are implanted into the first wafer in order to form a buried layer, and a second wafer is bonded to the bonding layer. The bonded first and second layers are heated and separated so that the second wafer has a top surface layer comprising Si from the first wafer. The top surface and the etch layer are then removed such that the epitaxial device layer remains on the second wafer to form the thin semiconductor layer.
Even though the process of using an etch stop can be effectively used to form thin device layers, it still remains a problem in the art of SOI technology to process non-SIMOX process SOI wafers without the need of an additional non-device quality supporting structure wafer. To further complicate matters, not only does the use of two wafers increase the costs of production but the additional steps of either etching or otherwise discarding the non-device quality wafer also adds to the costs and complexities of manufacturing the SOI wafers. The severe cost problems and process complexities associated with the production of SOI wafers can clearly be seen from the description of U.S. Pat. No. 5,882,987 and as well as in the Smart-Cut.TM. method of processing SOI wafers.
Thus, there is a need for a process that is capable of producing multiple SOI wafers in a single processing step without the need for additional non-device quality wafers. This process would preferably use only one wafer for each manufactured SOI wafer, and would greatly reduce the processing complexities and costs of manufacturing multiple SOI wafers in a single processing step.